• Pradosh Priyadarshan

Hardware Design with VHDL Design. Universal Asynchronous Receiver and Transmitter A serial communication protocol that sends parallel data through a serial line.

UART, Serial Port, RS-232 Interface Code in both VHDL and Verilog for FPGA Implementation Do you know how a UART works? If not, first brush up on the before continuing on. Have you considered how you might sample data with an FPGA? Think about data coming into your FPGA. Data can arrive by itself or it can arrive with a clock. When it arrives with a clock, it is call synchronous. When it arrives without a clock, it is called asynchronous.

A UART is an asynchronous interface. In any asynchronous interface, the first thing you need to know is when in time you should sample (look at) the data. If you do not sample the data at the right time, you might see the wrong data. In order to receive your data correctly, the transmitter and receiver must agree on the baud rate. The baud rate is the rate at which the data is transmitted.

For example, 9600 baud means 9600 bits per second. The code below uses a generic in VHDL or a parameter in Verilog to determine how many clock cycles there are in each bit.

This is how the baud rate gets determined. The FPGA is continuously sampling the line. Once it sees the line transition from high to low, it knows that a UART data word is coming. This first transition indicates the start bit. Once the beginning of the start bit is found, the FPGA waits for one half of a bit period. This ensures that the middle of the data bit gets sampled.

From then on, the FPGA just needs to wait one bit period (as specified by the baud rate) and sample the rest of the data. The figure below shows how the UART receiver works inside of the FPGA. First a falling edge is detected on the serial data line.

This represents the start bit. The FPGA then waits until the middle of the first data bit and samples the data.

It does this for all eight data bits. If you want to simulate your code (and you should) you need to use a. Luckily there is a test bench already created for you! This testbench below exercises both the Transmitter and the Receiver code.

It is programmed to work at 115200 baud. Note that this test bench is for simulation only and can not be synthesized into functional FPGA code. VHDL Implementation: VHDL Receiver (UARTRX.vhd): - - File Downloaded from - - This file contains the UART Receiver.

This receiver is able to - receive 8 bits of serial data, one start bit, one stop bit, - and no parity bit. When receive is complete orxdv will be - driven high for one clock cycle.

Pradosh Priyadarshan

Verilog Implementation: Verilog Receiver (uartrx.v): ////////////////////////////////////////////////////////////////////// // File Downloaded from ////////////////////////////////////////////////////////////////////// // This file contains the UART Receiver. This receiver is able to // receive 8 bits of serial data, one start bit, one stop bit, // and no parity bit. When receive is complete orxdv will be // driven high for one clock cycle.